Processor arrangements of the aforementioned type contain functional units that operate in parallel to one another and that are controlled at every clock cycle by an instruction word. The particular instruction word is extracted from a program word that is taken from a program memory.
For their part, the instruction words consist of a plurality of instruction word parts, where each individual instruction word part serves to control one functional unit.
To improve the performance of processor arrangements, the goal is an increase in the processing width, which makes it necessary to increase the number of functional units. In general, this increases the bit width of the instruction words and thus also of the program words. The consequence of this is the provision of corresponding storage space in the program memory, which occupies the majority of the area on the semiconductor chip.
Since the size of the program words determines the size of the program memory, the goal is to reduce the size of the program words in order to reduce the need for memory space. A number of compression methods for this purpose are known. The most obvious method is described in the report by H. Weiss and G. Fettweis, [in English:] “Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors” (Proceedings of the 3rd International Workshop on Signal and Image Processing IWSIP '96, pages 517 to 520).
In this method, the program words are assembled from sequential primary instruction words in such a way that secondary instruction words can be subsequently reproduced therefrom in that a secondary instruction word (VLIW), once it has been created, is written to an instruction word memory, and, in order to produce the next secondary instruction word, only those instruction word parts in the stored secondary instruction word are exchanged which differ between the stored secondary instruction word and the secondary instruction word to be generated. Consequently, the program word need only contain the information specifying which instruction word part differs and with what content it differs.
It is thus possible to design the program words to be very narrow and thus save memory space.
However, when there are great differences between the stored secondary instruction word and the secondary instruction word to be created, the width of the program word must be increased if these relatively great differences occur frequently, which entails the disadvantage of a relatively large memory space, or else the differences must be distributed over multiple program words. Thus, the secondary instruction word must be created from multiple program words over multiple clock cycles. This results in the disadvantage that it requires a relatively long time.
Consideration is now being given to ways of overcoming this disadvanatge. In particular, attention is directed to specific ways of increasing the operating speed in an application while retaining a small program word widths.